1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to a clock divider employing true single phase logic.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Clocking circuits are employed in a wide variety of digital circuits and devices to synchronize operations across devices, circuit boards, or integrated circuits. For a variety of reasons, however, a single clock frequency is often not sufficient to accommodate every device or circuit in a complex computer or other electronic device. For this reason, many computers or digital devices employ multiple clock signals at different frequencies. For example, in some computers, a central processing unit may be clocked by a first clock signal at a first clock frequency, while the memory is clocked by a second clock signal at a second, different clock frequency. Rather than employ multiple clocks, most systems derive alternate clock frequencies from a single base clock frequency, which is typically the clock signal used for the central processing unit. Implementing clock dividers provides one technique for performing this derivation.
As most people are aware, computers and computer-related technologies have been steadily increasing in computing power and complexity over the past several years. One popular technique for increasing the computing power of a computer is to increase the clock speed of the central processing unit within the computer. For example, many central processing units now operate with clock speeds of two to four gigahertz or more. Most conventional clock dividers, however, are not suitable for dividing clock signals in this frequency range, because most conventional clock dividers employ static logic gates and flip-flops that have internal logic gate delays and set-up times that are slower than the period (i.e., 1/frequency) of clock signals above two gigahertz. In other words, conventional, static-logic-based clock dividers are often too slow to accurately divide clock signals with frequencies above two gigahertz.
Embodiments of the present invention may address one or more of the problems set forth above.